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VG3617801CT bảng dữ liệu(PDF) 21 Page - Vanguard International Semiconductor

tên linh kiện VG3617801CT
Giải thích chi tiết về linh kiện  16Mb CMOS Synchronous Dynamic RAM
PDF  68 Pages
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nhà sản xuất  VML [Vanguard International Semiconductor]
Trang chủ  http://www.vis.com.tw
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VG3617801CT bảng dữ liệu(HTML) 21 Page - Vanguard International Semiconductor

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Document:1G5-0133
Rev.1
Page 21
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
9.3 WRITE to READ Command Interval
The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data pre-
ceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior
to the first DOUT.
WRITE to READ Command Interval
9.4 READ to WRITE Command Interval
During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance
using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command.
This restriction is necessary to avoid a data bus conflict.
Burst lengh=4
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
QB0
QB3
QB2
QB1
WRITE A
Write A
T0
T1
T2
T3
T4
T5
T6
T7
T8
QB0
QB3
QB2
QB1
1 cycle
Read B
DA0
Read B
DA0
Hi-Z
Hi-Z



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