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VG26VS18165C bảng dữ liệu(PDF) 11 Page - Vanguard International Semiconductor

tên linh kiện VG26VS18165C
Giải thích chi tiết về linh kiện  1,048,576 x 16 - Bit CMOS Dynamic RAM
PDF  27 Pages
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nhà sản xuất  VML [Vanguard International Semiconductor]
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VG26VS18165C bảng dữ liệu(HTML) 11 Page - Vanguard International Semiconductor

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Document:1G5-0147
Rev.1
Page 11
VIS
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Read Cycle
Write Cycle
Read- Modify- Write Cycle
Parameter
Symbol
VG26(V)(S)18165C
Unit
Notes
-5
-6
Min
Max
Min
Max
Access time from RAS
tRAC
-
50
-
60
ns
13
Access time from LCAS / UCAS
tCAC
-
13
-
15
ns
14, 15
Access time from column address
tAA
-
25
-
30
ns
15, 16
Access time from OE
tOEA
-
12
-
15
ns
Read command setup time
tRCS
0
-
0
-
ns
8
Read command hold time to LCAS / UCAS
tRCH
0
-
0
-
ns
11, 17
Read command hold time to RAS
tRRH
10
-
10
-
ns
17
Output buffer turn-off time
tOFF
0
12
0
15
ns
18
Output buffer turn-off time from OE
tOEZ
0
12
0
15
ns
18
Parameter
Symbol
VG26(V)(S)18165C
Unit
Notes
-5
-6
Min
Max
Min
Max
Write command setup time
tWCS
0
-
0
-
ns
8, 19
Write command hold time
tWCH
8
-
10
-
ns
Write command pulse width
tWP
8
-
10
-
ns
Write command to RAS lead time
tRWL
13
-
15
-
ns
Write command to LCAS / UCAS lead time
tCWL
8
-
10
-
ns
20
Data-in setup time
tDS
0
-
0
-
ns
21
Data-in hold time
tDH
8
-
10
-
ns
21
WE to Data-in delay
tWED
10
-
10
-
ns
Parameter
Symbol
VG26(V)(S) 18165C
Unit
Notes
-5
-6
Min
Max
Min
Max
Read-modify- write cycle time
tRWC
108
-
133
-
ns
RAS to WE delay time
tRWD
64
-
77
-
ns
19
LCAS / UCAS to WE dealy time
tCWD
26
-
32
-
ns
19
Column address to WE delay time
tAWD
39
-
47
-
ns
19
OE hold time from WE
tOEH
8
-
10
-
ns



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