HMC702LP6CE datasheet(32/46 Pages) HITTITE

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HMC702LP6CE

v05.0110

14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER

Serial Port WRITE Operation

aVDD = DVDD = 3V ±10%, aGnD = DGnD = 0V

Table 4. Timing Characteristics

Parameter

Conditions

Min.

Typ.

Max

Units

sen to scLK setup time

nsec

sDi to scLK setup time

nsec

sDi to cLK hold time

nsec

scLK high duration

nsec

scLK low duration

nsec

sen high duration

640

nsec

sen low duration

nsec

a typical Write cycle is shown in figure 29.

a. the Master (host) both asserts sen (serial Port enable) and clears sDi to indicate a Write

cycle, followed by a rising edge of scLK.

b. the slave (synthesizer) reads sDi on the 1st rising edge of scLK after sen. sDi low initiates

the Write cycle (/Wr)

c. host places the six address bits on the next six falling edges of scLK, MsB first.

d. slave registers the address bits in the next six rising edges of scLK (2-7).

e. host places the 24 data bits on the next 24 falling edges of scK, MsB first .

f. slave registers the data bits on the next 24 rising edges of scK (8-31).

g. sen is de-asserted on the 32nd falling edge of scLK.

h. the 32nd rising edge of scLK completes the cycle

Figure 29. Serial Port Timing Diagram - WRITE

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