HMC702LP6CE datasheet(23/46 Pages) HITTITE

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HMC702LP6CE

v05.0110

14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER

a normal 3 sigma peak-to-peak variation in the arrival time therefore would be

if the synthesizer was in fractional mode, the fractional modulation of the Vco divider will dominate the jitter. the exact

standard deviation of the divided Vco signal will vary based upon the modulator chosen, however a typical modulator

will vary by about ±3 Vco periods, ±4 Vco periods, worst case.

if, for example, a nominal Vco at 5 Ghz is divided by 100 to equal the reference at 50 Mhz, then the worst case

division ratios will vary by 100±4. hence the peak variation in the arrival times caused by Δ∑ modulation of the

fractional synthesizer at the reference will be

(eQ 11)

PFD Jitter and Lock Detect Background (Continued)

in this example, tjΔ∑pk = ±200 ps(108-92)/2 = ±1600 psec. if we note that the distribution of the delta sigma modulation

is approximately gaussian, we could approximate tjΔ∑pk as a 3 sigma jitter, and hence we could estimate the rms jitter

of the Δ∑ modulator as about 1/3 of tjΔ∑pk or about 532 psec in this example.

hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the Vco would be given

by the rms sum , where

(eQ 12)

in this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at

the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation.

Bottom line, we have to expect about ±1.6 nsec of normal variation in the phase detector arrival times when in

fractional mode. in addition, lower Vco frequencies with high reference frequencies will have much larger variations.,

for example, a 1 Ghz Vco operating at near the minimum nominal divider ratio of 72, would, according to (eQ 11),

exhibit about ±4 nsec of peak variation at the phase detector, under normal operation. the lock detect circuit must not

confuse this modulation as being out of lock.

PFD Lock Detect

lkd_en (Reg01h<11> table 12) enables the lock detect functions of the hMc702LP6ce.

the Lock Detect circuit in the hMc702LP6ce places a one shot window around the reference. the one shot window

may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer.

clearing lkd_ringosc_mono_select (Reg1Ah<14> table 36) will result in a nominal ±10nsec ‘analog’ window of fixed

length, as shown in figure 21. setting lkd_ringosc_mono_select will result in a variable length ’digital’ widow. the

digital one shot window is controlled by lkd_ringosc_cfg (Reg1Ah<16:15>). the resulting lock detect window period is

then generated by the number of ring oscillator periods defined in lkd_monost_duration Reg1Ah<18:17> (table 36).

the lock detect ring oscillator may be observed on the GPo2 port by setting ringosc_testmode (Reg1Ah<19> table

36) and configuring the gpo_sel<3:0> = 0111 in (Reg1Bh table 37). Lock detect does not function when this test mode

is enabled.

lkd_wincnt_max (Reg1Ah<9:0> table 36) defines the number of consecutive counts of the Vco that must land inside

the lock detect window to declare lock. if for example we set lkd_wincnt_max = 1000 , then the Vco arrival would

have to occur inside the selected lock widow 1000 times in a row to be declared locked. When locked the Lock Detect

flag ro_lock_detect (Reg1Fh<0> table 41) will be set. a single occurrence outside of the window will result in clearing

the Lock Detect flag, ro_lock_detect.

±3

√ 2Tjpn = 0.756 ps

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