PAC407BCA/PAC407BCW

CMOS Image Sensor IC

Version 1.7, 13 Sep

2004

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

12

5.2. Data Transfer Format

5.2.1. Master transmits data to slave (write cycle)

S: Start

A: Acknowledge by slave

P: Stop

RW: The LSB of 1ST byte to decide whether current cycle is read or write cycle.

If RW=1 that means read cycle, if RW=0 that means write cycle.

SUBADDRESS:

The

address

values

of

PAC407

internal

control

registers

(Please refer to PAC407 register description)

During the write cycle, the master generates start condition and then places the 1st byte data that

combined slave address (7 bits) with a read/write control bit on SDA line. After slave(PAC407) issues

acknowledgment, the master places 2nd byte (sub-address) data on SDA line. And then following the

slave’s( PAC407) acknowledgment, the master places the 8 bits data on SDA line and transmit to PAC407

control register (address was assigned by 2nd byte). After PAC407 issue acknowledgment, the master can

generate a stop condition to end this write cycle. In the condition of multi-byte write, the PAC407

sub-address will be increased automatically after each DATA byte has been transferred. The Data and A

cycles are repeated until last byte write. Every control registers value inside PAC407 can be programming

via this way. (Please refer to Figure 5.3.)

5.2.2. Slave transmits data to master (read cycle)

The sub-address was assigned by previous write cycle

The sub-address is automatically increased after each byte read

Am : Acknowledged by master

Note there is no acknowledgment from master after last byte read

S

SLAVE ADDRESS

(7 BITS)

RW

A

DATA (8 BIT)

Am

DATA

1

P

1ST BYTE

2ND BYTE

n BYTE

NO ACK IN LAST

BYTE

Am

DATA

S

SLAVE ID (7 BIT)

RW

A

SUBADDRESS (8 BIT)

A

DATA

P

A

1ST BYTE

2ND BYTE

n BYTEs + A

MSB

LSB=0

A

DATA

S

SLAVE ID (7 BIT)

RW

A

SUBADDRESS (8 BIT)

A

DATA

P

A

1ST BYTE

2ND BYTE

n BYTEs + A

MSB

LSB=0

A

DATA