PixArt Imaging Inc.

PAC107

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30

PixArt Imaging Inc.

V1.4, Aug, 2005

Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from

the TH0 register. TL0 overflow sets the timer overflow flag (TF0) in the TCON register

and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged.

Timer 0/ Mode 3(Two 8-bit Timers)

Mode 3: TL0 and TH0 operate as 8-bit timers independently. Counter TL0 is configured by

running at frequency= Fosc/12) and takes over by timer 1 interrupt (TF1) and run control

bits(TR1). Thus, operation of timer 1 is restricted when timer 0 is in mode 3.

Timer 1

Timer 1 can be a timer or event counter in three modes of operation. The configuration for

12

0

1

XTAL1

Tx

TLx

(8 Bits)

Overflow

Interrupt

Request

TFx

GATEx

TRx

x = 0 or 1

THx

(8 Bits)

Reload

C/ Tx

INTx

Timer 0/1 in Mode 2,Auto-Reload

12

0

1

XTAL1

T0

TL0

(8 Bits)

Overflow

Interrupt

Request

GATE0

TR0

1/12 Fosc

TH0

(8 Bits)

TF0

TF1

1/12 Fosc

TR1

Interrupt

Request

Overflow

C/T0

INT0

Timer 0 in Mode 3 Two 8-bit Timers