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AM1808AZCE4 bảng dữ liệu(PDF) 58 Page - Texas Instruments

tên linh kiện AM1808AZCE4
Giải thích chi tiết về linh kiện  AM1808 ARM Microprocessor
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AM1808AZCE4 bảng dữ liệu(HTML) 58 Page - Texas Instruments

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AM1808
SPRS653 – FEBRUARY 2010
www.ti.com
Table 3-27. General Purpose Input Output Terminal Functions (continued)
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
GP8
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]
G1
I/O
CP30]
C
/ PRU1_R31[27]
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
G2
I/O
CP[30]
C
PRU1_R31[26]
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
J4
I/O
CP[30]
C
PRU1_R31[25]
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
G3
I/O
CP[30]
C
PRU1_R31[24]
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
F1
I/O
CP[31]
C
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
F2
I/O
CP[31]
C
PRU1_R31[7]
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
H4
I/O
CP[31]
C
PRU1_R31[6]
GPIO Bank 8
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
G4
I/O
CP[31]
C
PRU1_R31[5]
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0
F3
I/O
CP[6]
A
SPI0_SOMI /EPWMSYNCI / GP8[6] / MII_RXER
C16
I/O
CP[7]
A
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS
C18
I/O
CP[7]
A
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3]
C19
I/O
CP[8]
A
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]
D18
I/O
CP[8]
A
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /
E17
I/O
CP[9]
A
SATA_MP_SWITCH
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0]
D16
I/O
CP[9]
A
/SATA_CP_DET
RTCK/ GP8[0] (1)
K17
I/O
IPD
B
(1)
GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
58
Device Overview
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): AM1808



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