DM9013 datasheet(32/75 Pages) DAVICOM

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DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

6.50 Per Port Block Unknown ports Control Register (6BH)

Bit

Name

Default

Description

7:4

RESERVED

PH0,RW Reserved

3:0

BLK_UKP

PH0,RW Ports of unknown packet be blocked

6.51 Per Port Priority Queue Control Register (6DH)

Bit

Name

Default

Description

TAG_OUT

PE0,RW

Output Packet Tagging Enable

PRI_DIS

PE0,RW

Priority Queue Disable

WFQUE

PE0,RW

8:4:2:1

0: queue 3 > 2 > 1 > 0

1: 8:4:2:1

TOS_PRI

PE0,RW

Priority ToS over VLAN

TOS_OFF

PE0,RW

ToS Priority Classification disable

PRI_OFF

PE0,RW

802.1 p Priority Classification disable

1:0

P_PRI

PE0,RW

Port Base priority

00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3

6.52 Per Port VLAN Tag Low Byte Register (6EH)

Bit

Name

Default

Description

7:0

VID70

PE01,RW

VID[7:0]

6.53 Per Port VLAN Tag High Byte Register (6FH)

Bit

Name

Default

Description

7:5

PRI

PE0,RW

Tag [15:13]

CFI

PE0,RW

Tag[12]

3:0

VID118

PE0,RW

VID[11:8]

6.54 MIB counter Port Index Register (80H)

Bit

Name

Default

Description

READY

P0,RO

MIB counter data is ready

When this register is written with INDEX data, this bit is cleared and the MIB

counter reading is in progress. After end of read MIB counter, the MIB data is

loaded into register 81H~84H, and this bit is set to indicate that the MIB data is

ready.

6:5

reserved

0,RO

Reserved

4:0

INDEX

PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h.

Write the MIB counter index to this register before read them.

6.55 MIB counter Data Register (81H~84H)

Bit

Name

Default

Description

81H

Counter0

X,RO

Counter’s data bit 7~0

82H

Counter1

X,RO

Counter’s data bit 15~8

83H

Counter2

X,RO

Counter’s data bit 23~16

84H

Counter3

X,RO

Counter’s data bit 31~24

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