DM9013 datasheet(21/75 Pages) DAVICOM

21 / 75 page

DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

6.1 Network Control Register (00H)

Bit

Name

Default

Description

RESERVED

0,RO

Reserved

RESERVED

P0,WO

Reserved

CLR1

PH0,RW

0: REG. 01H auto-cleared after read

1: REG. 01H cleared by writing 1 to respected bit.

4:2

RESERVED

0,RO

Reserved

LBK

PH0,

Loopback test Mode

RST

PH0,RW

Software reset and auto clear after 10us

6.2 Network Status Register (01H)

Bit

Name

Default

Description

7:6

RESERVED

0,RO

Reserved

RESERVED

PH0,

Reserved

RESERVED

0,RO

Reserved

TX2END

PHS0,

RW/C1

TX Packet 2 Complete Status.

This bit is set after transmit completion of packet index 2

If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by

read or write 1.

TX1END

PHS0,

RW/C1

TX Packet 1 Complete status.

This bit is set after transmit completion of packet index 1

If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by

read or write 1.

1:0

RESERVED

0,RO

Reserved

6.3 TX Control Register (02H)

Bit

Name

Default

Description

7:4

RESERVED

0,RO

Reserved

CRC_DIS2

PHS0,RW CRC Appends Disable for Packet Index 2

RESERVED

0,RO

Reserved

CRC_DIS1

PHS0,RW CRC Appends Disable for Packet Index 1

TXREQ

PHS0,RW TX Request. Auto clears after transmit completely

6.4 RX Control Register (05H)

Bit

Name

Default

Description

HASHALL

PHS0,RW

Filter All address in Hash Table

RESERVED PHS0,RW

Reserved

RESERVED PHS0,RW

Reserved

RESERVED PHS0,RW

Reserved

ALL

PHS0,RW

Pass All Multicast Packets

RESERVED PHS0,RW

Reserved

PRMSC

PHS0,RW

Promiscuous Mode

RXEN

PHS0,RW

RX Enable

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