AS8218 datasheet(93/123 Pages) AMSCO

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Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 93 of 123

Watchdog Timer (WDT)

A watchdog timer is provided on-chip to automatically initiate a system reset if a ‘hold-off’ signal is not detected

within a predefined timeout period, by the watchdog.

The watchdog timer consists of a programmable timer driven either by the Mclk (main oscillator output

frequency), or the MCU clock (microcontroller unit clock). The watchdog timer timeout period is dependent

upon the programming of the WDTCLK register. When the watchdog times out, a reset signal is generated

which is OR-ed with the main system reset. Thus a watchdog timer reset is identical to a power on reset.

If the watchdog timer function is required, the watchdog is enabled by setting the WDTE register LSB (Bit 0).

As soon as this bit is enabled, the program must periodically access the WDTCLK register (either read or write)

to prevent the watchdog timer from timeout and thus resetting the device.

Address

Reset Value

Description

WDTE

9180h

xxxx.xxx0b

Enables or disables the watchdog timer function

0: watchdog disabled

1: watchdog enabled

WDTCLK[1:0]

9181h

xxxx.xxx00b

A read or write access clears the watchdog timer. Writing

bits [1:0] selects the clock source.

x ........Don’t care

Watchdog Timer Enable Register (WDTE)

MSB

LSB

WDTE0

Bit

Symbol Function

Not used

WDTE0 Disables and enables the watchdog timer function

0: watchdog disabled

1: watchdog enabled

The watchdog timer has a selectable counter length of 18 bit, 20 bit or 22 bit for the Mclk and 18 bits for the

mcu_clk. It should be noted that while the Mclk has a fixed frequency, depending on the crystal frequency, the

MCU clock is programmable, being divisible by 1 to 128, in binary steps (see MCUCLKDIV Register

(‘mcu_clk’)). The timeout periods below assume the Mclk = 3.579545MHz (fixed crystal frequency).

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