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AD9992BBCZ bảng dữ liệu(PDF) 68 Page - Analog Devices

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Giải thích chi tiết về linh kiện  12-Bit CCD Signal Processor with Precision Timing Generator
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AD9992BBCZ bảng dữ liệu(HTML) 68 Page - Analog Devices

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AD9992
Rev. C | Page 68 of 92
Table 27. Standby Mode Operation (Standby Polarities for XV, XSUBCK, GPO Outputs Are Programmable)
I/O Block
Standby3 (Default)1, 2
OUTCONTROL = Low2
Standby23, 4
Standby13, 4
AFE
Off
No change
Off
Only REFT, REFB on
Timing Core
Off
No change
Off
On
CLO Oscillator
Off
No change
Off
On
CLO
Low
No change
Low
Running
H1
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
H2
High-Z
High
High (4.3 mA)
High (4.3 mA)
H3
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
H4
High-Z
High
High (4.3 mA)
High (4.3 mA)
H5
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
H6
High-Z
High
High (4.3 mA)
High (4.3 mA)
H7
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
H8
High-Z
High
High (4.3 mA)
High (4.3 mA)
HL
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
RG
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
VD
Low
VDHDPOL value
VDHDPOL value
Running
HD
Low
VDHDPOL value
VDHDPOL value
Running
DCLK
Low
Running
Low
Running
DOUT
Low
Low
Low
Low
XV1 to XV24
Low
Low
Low
Low
XSUBCK
Low
Low
Low
Low
GPO1 to GPO8
Low
Low
Low
Low
1 To exit Standby3, write 00 to STANDBY (Address 0x00, Bits [1:0]), and then reset the timing core after 500 μs to guarantee proper settling of the oscillator and external crystal.
2 Standby3 mode takes priority over OUTCONTROL for determining the output polarities.
3 These polarities assume OUTCONTROL = high because OUTCONTROL = low takes priority over Standby1 and Standby2.
4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).



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