AD9992BBCZ datasheet(59/92 Pages) AD

tên linh kiện	AD9992BBCZ

Giải thích chi tiết về linh kiện	12-Bit CCD Signal Processor with Precision Timing Generator

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AD9992

Rev. C | Page 59 of 92

SUSPEND

SYNC

NOTES

1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.

2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).

3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).

4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT.

5. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.

6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.

FIELD

DESIGNATOR

H1 TO H4, RG,

XV1 TO XV24

VSG, SUBCK

Figure 66. Default Mode 1

1FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC.

2RISING EDGE RESETS COUNTERS.

3VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE.

4SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE.

5XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY.

SYNC

VDLEN

SCP

XV1 TO XV24

Figure 67. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value

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