MPC8536AVTATH datasheet(96/128 Pages) FREESCALE

96 / 128 page

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

High-Speed Serial Interfaces

Freescale Semiconductor

Figure 62 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC

levels of the clock driver chip is compatible with MPC8536E SerDes reference clock input’s DC requirement.

Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 63 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock

driver’s common mode voltage is higher than the MPC8536E SerDes reference clock input’s allowed range (100 to 400mV),

AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-

Ω termination resistor. It also

assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external

component.

Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

CLK_Out

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8536E

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