công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

MPC8536AVTATH bảng dữ liệu(PDF) 80 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8536AVTATH
Giải thích chi tiết về linh kiện  PowerQUICC??III Integrated Processor Hardware Specifications
PDF  128 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8536AVTATH bảng dữ liệu(HTML) 80 Page - Freescale Semiconductor, Inc

Back Button MPC8536AVTATH Datasheet HTML 76Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 77Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 78Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 79Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 80Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 81Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 82Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 83Page - Freescale Semiconductor, Inc MPC8536AVTATH Datasheet HTML 84Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 80 / 128 page
background image
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Serial ATA (SATA)
Freescale Semiconductor
80
2.16.1
Requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in Table 59.
Figure 49. Reference Clock Timing Waveform
Table 59. Reference Clock Input Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Notes
SD2_REF_CLK/_B reference clock cycle time
tCLK_REF
100
—
150
MHz
1
SD2_REF_CLK/_B frequency tolerance
tCLK_TOL
–350
0
+350
ppm
—
SD_REF_CLK/_B rise/fall time (80%-20%)
tCLK_RISE/tCLK_FALL
—
—
1
ns
—
SD_REF_CLK/_B duty cycle (@50% X2VDD)
tCLK_DUTY
45
50
55
%
—
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
tCLK_CJ
——
100
ps
—
SD_REF_CLK/_B phase jitter (peak-to-peak)
tCLK_PJ
–50
—
+50
ps
2,3
Note:
1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
TH
TL
Ref_CLK



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com