MPC5634M datasheet(26/118 Pages) FREESCALE

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MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Overview

Freescale Semiconductor

NOTE

In the VertiCal package, the full Nexus Auxiliary port shares balls with the addresses of the

calibration bus. Therefore multiplexed address/data bus mode must be used for the

calibration bus when using full width Nexus trace in VertiCal assembly.

The following features are implemented:

•

5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

— Always available in production package

— Supports both JTAG Boundary Scan and debug modes

— 3.3 V interface

— Supports Nexus class 1 features

— Supports Nexus class 3 read/write feature

•

9-pin Reduced Port interface in 144 LQFP production package

— Alternate function as IO

— 5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface

— Auxiliary Output port

– 1 MCKO (message clock out) pin

– 4 MDO (message data out) pins

–2 MSEO (message start/end out) pins

–1 EVTO (event out) pin

— Auxiliary input port

– 1 EVTI (event in) pin

•

17-pin Full Port interface in VertiCal calibration package

— 3.3 V interface

— Auxiliary Output port

– 1 MCKO (message clock out) pin

– 4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8 extra full port pins shared with

calibration bus

–2 MSEO (message start/end out) pins

–1 EVTO (event out) pin

— Auxiliary input port

– 1 EVTI (event in) pin

•

Host processor (e200) development support features

— IEEE-ISTO 5001-2003 standard class 2 compliant

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires

between the discontinuities. Thus, static code may be traced.

— Watchpoint trigger enable of program trace messaging

— Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a

specific value to a memory location

– 4 data value breakpoints

–CPU only

– Detects ‘equal’ and ‘not equal’

– Byte, half word, word (naturally aligned)

NOTE

This feature is imprecise due to CPU pipelining.

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