ATmega64A datasheet(383/392 Pages) ATMEL

383 / 392 page

383

8160C–AVR–07/09

ATmega64A

NOP

; no operation

NOP

; no operation

SEI

; clear global interrupt enable

Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega64A is the only device in the scan chain, the problem is not visible.

–

Select the Device ID Register of the ATmega64A by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega64A while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega64A must be the first device in the chain.

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

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