ATmega64A datasheet(332/392 Pages) ATMEL

tên linh kiện	ATmega64A

Giải thích chi tiết về linh kiện	8-bit Microcontroller with 64K Bytes In-System Programmable Flash

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332

8160C–AVR–07/09

ATmega64A

2. Required only for fSCL > 100 kHz.

3. C

b = capacitance of one bus line in pF.

4. f

CK = CPU clock frequency

5. This requirement applies to all ATmega64A Two-wire Serial Interface operation. Other devices connected to the Two-wire

Serial Bus need only obey the general f

SCL requirement.

6. The actual low period generated by the ATmega64A Two-wire Serial Interface is (1/f

SCL - 2/fCK), thus fCK must be greater than

6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega64A Two-wire Serial Interface is (1/f

SCL - 2/fCK), thus the low time require-

ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega64A devices connected to the bus may

communicate at full speed (400 kHz) with other ATmega64A devices, as well as any other device with a proper tLOW accep-

tance margin.

Figure 28-3. Two-wire Serial Bus Timing

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

ATmega64A bảng dữ liệu(PDF) 332 Page - ATMEL Corporation