ATmega64A datasheet(310/392 Pages) ATMEL

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310

8160C–AVR–07/09

ATmega64A

27.8

SPI Serial Programming Pin Mapping

Even though the SPI Programming interface re-uses the SPI I/O module, there is one important

difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not

used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-

ming mode as shown in Table 27-13.

Figure 27-10. SPI Serial Programming and Verify

(1)

Note:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck

12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck

12 MHz

27.8.1

SPI Serial Programming Algorithm

When writing serial data to the ATmega64A, data is clocked on the rising edge of SCK.

When reading data from the ATmega64A, data is clocked on the falling edge of SCK. See Figure

27-11 for timing details.

To program and verify the ATmega64A in the SPI Serial Programming mode, the following

sequence is recommended

Table 27-13. Pin Mapping SPI Serial Programming

Symbol

Pins

I/O

Description

MOSI (PDI)

PE0

Serial Data In

MISO (PDO)

PE1

Serial Data Out

SCK

PB1

Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

PE0

PE1

PB1

+2.7 - 5.5V

AVCC

+2.7 - 5.5V (2)

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