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ATmega64A bảng dữ liệu(PDF) 270 Page - ATMEL Corporation |
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ATmega64A bảng dữ liệu(HTML) 270 Page - ATMEL Corporation |
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270 / 392 page ![]() 270 8160C–AVR–07/09 ATmega64A Table 25-5. Boundary-scan Signals for the ADC(1) Signal Name Direction as Seen from the ADC Description Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC COMP Output Comparator Output 0 0 ACLK Input Clock signal to gain stages implemented as Switch-cap filters 00 ACTEN Input Enable path from gain stages to the Comparator 00 ADCBGEN Input Enable Band-gap reference as negative input to Comparator 00 ADCEN Input Power-on signal to the ADC 00 AMPEN Input Power-on signal to the gain stages 00 DAC_9 Input Bit nine of digital value to DAC 11 DAC_8 Input Bit eight of digital value to DAC 00 DAC_7 Input Bit seven of digital value to DAC 00 DAC_6 Input Bit six of digital value to DAC 00 DAC_5 Input Bit five of digital value to DAC 00 DAC_4 Input Bit four of digital value to DAC 00 DAC_3 Input Bit three of digital value to DAC 00 DAC_2 Input Bit two of digital value to DAC 00 DAC_1 Input Bit 1 of digital value to DAC 00 DAC_0 Input Bit 0 of digital value to DAC 00 EXTCH Input Connect ADC channels 0 - 3 to bypass path around gain stages 11 G10 Input Enable 10x gain 0 0 G20 Input Enable 20x gain 0 0 |
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