ATmega64A datasheet(209/392 Pages) ATMEL

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209

8160C–AVR–07/09

ATmega64A

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

21.6

Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in

order to detect actions on the TWI bus.

When the TWINT flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR registers.

Figure 21-10 is a simple example of how the application can interface to the TWI hardware. In

this example, a Master wishes to transmit a single data byte to a Slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission

The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instructing the TWI hardware to transmit a START

condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

START

SLA+W

Data

STOP

1. Application writes

to TWCR to initiate

transmission of

START

2. TWINT set.

Status code indicates

START condition sent

4. TWINT set.

Status code indicates

SLA+W sent, ACK

received

6. TWINT set.

Status code indicates

data sent, ACK received

3. Check TWSR to see if START was

sent. Application loads SLA+W into

TWDR, and loads appropriate control

signals into TWCR, making sure that

TWINT is written to one, and

TWSTA is written to zero.

5. Check TWSR to see if SLA+W was

sent and ACK received.

Application loads data into TWDR,

and loads appropriate control signals

into TWCR, making sure that

TWINT is written to one

7. Check TWSR to see if data was sent

and ACK received. Application loads

appropriate control signals to send

STOP into TWCR, making sure that

TWINT is written to one

TWI bus

Indicates

TWINT set

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