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ATmega64A bảng dữ liệu(PDF) 160 Page - ATMEL Corporation |
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ATmega64A bảng dữ liệu(HTML) 160 Page - ATMEL Corporation |
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160 / 392 page  160 8160C–AVR–07/09 ATmega64A 17.9.2 TCNT2 – Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. 17.9.3 OCR2 – Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. 17.9.4 TIMSK – Timer/Counter Interrupt Mask Register • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs, for example, when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. 17.9.5 TIFR – Timer/Counter Interrupt Flag Register • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. Bit 7654 3210 0x24 (0x44) TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 0000 Bit 7654 3210 0x23 (0x43) OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 0000 Bit 7 65 4 3 21 0 0x37 (0x57) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7654 3210 0x36 (0x56) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 0000 |
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