ATXMEGA64A1 datasheet(84/99 Pages) ATMEL

84 / 99 page

8067I–AVR–04/09

XMEGA A1

35. Errata

35.1

ATxmega128A1 rev. H

• Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

• DAC is nonlinear and inaccurate when reference is above 2.4V or V

CC - 0.6V

• ADC gain stage output range is limited to 2.4V

• The ADC has up to ±2 LSB inaccuracy

• TWI, a general address call will match independent of the R/W-bit value

• TWI, the minimum I2C SCL low time could be violated in Master Read mode

• TWI, the address-mask features is missing

• Setting HIRES PR bit makes PWM output unavailable

• BOD will be enabled after any reset

• Propagation delay analog Comparator increasing to 2 ms at -40°C

• Sampled BOD in Active mode will cause noise when bandgap is used as reference

• Default setting for SDRAM refresh period too low

• Flash Power Reduction Mode can not be enabled when entering sleep mode

• JTAG enable does not override Analog Comparator B output

• Bandgap measurement with the ADC is non-functional when V

CC is below 2.7V

• DAC refresh may be blocked in S/H mode

Bandgap voltage input for the ACs cannot be changed when used for both ACs

simultaneously

If the bandgap voltage is selected as input for one Analog Comparator (AC) and then

selected/deselected as input for the another AC, the first comparator will be affected for up

to 1 us and could potentially give a wrong comparison result.

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both

ACs before enabling any of them.

DAC is nonlinear and inaccurate when reference is above 2.4V or Vcc-0.6V

Using the DAC with a reference voltage above 2.4V or Vcc-0.6Vgive inaccurate output when

converting codes that give below 0.75V output:

– ±10 LSB for continuous mode

– ±20 LSB for Sample and Hold mode

Problem fix/Workaround

None, avoid using a voltage reference above 2.4V or Vcc-0.6V

ADC gain stage output range is limited to 2.4 V

The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential

input will only give correct output when below 2.4 V/gain. For the available gain settings, this

gives a differential input range of

–

gain:

2.4

–

gain:

1.2

–

gain:

0.6

ATXMEGA64A1 bảng dữ liệu(PDF) 84 Page - ATMEL Corporation

ATXMEGA64A1 bảng dữ liệu(HTML) 84 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

bảng dữ liệu tải về

Link URL