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ATtiny167-ESSZ bảng dữ liệu(PDF) 58 Page - ATMEL Corporation |
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ATtiny167-ESSZ bảng dữ liệu(HTML) 58 Page - ATMEL Corporation |
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58 / 282 page ![]() 58 7728D–AVR–07/09 ATtiny87/ATtiny167 • Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. • Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 6-2 on page 58. Table 6-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at Vcc = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.0 s 1 0 0 1 1024K (1048576) cycles 8.0 s 10 10 Reserved 10 11 11 00 11 01 11 10 11 11 |
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