ATtiny167-ESSZ datasheet(171/282 Pages) ATMEL

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171

7728D–AVR–07/09

ATtiny87/ATtiny167

15.5.4

Configuration

Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the con-

troller in the following configuration (Table 15-3):

The LIN configuration is independent of the programmed LIN protocol.

The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this

mode, the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same

scheme is available in UART mode.

Figure 15-6. Listening Mode

15.5.5

Busy Signal

LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by

hardware. It signals that the controller is busy with LIN or UART communication.

15.5.5.1

Busy Signal in LIN Mode

Figure 15-7. Busy Signal in LIN Mode

Table 15-3.

Configuration Table versus Mode

Mode

LCONF[1..0]

Configuration

LIN

LIN standard configuration (default)

01 b

No CRC field detection or transmission

Frame_Time_Out disable

Listening mode

UART

00 b

8-bit data, no parity & 1 stop-bit

8-bit data, even parity & 1 stop-bit

8-bit data, odd parity & 1 stop-bit

11 b

Listening mode, 8-bit data, no parity & 1 stop-bit

TXLIN

RXLIN

internal

Tx LIN

internal

Rx LIN

LISTEN

BREAK

Field

SYNC

Field

CHECKSUM

Field

DATA-0

Field

IDENTIFIER

PROTECTED

DATA-n

Field

RESPONSE

HEADER

FRAME SLOT

LIN bus

LIDOK

Node providing the master task

Node providing a slave task

LCMD=Tx Header

LTXOK or LRXOK

LCMD=Tx or Rx Response

1) LBUSY

3) LBUSY

2) LBUSY

Node providing neither the master task, neither a slave task

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