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ATtiny167-ESSZ bảng dữ liệu(PDF) 148 Page - ATMEL Corporation

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Giải thích chi tiết về linh kiện  8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller
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148
7728D–AVR–07/09
ATtiny87/ATtiny167
13.3
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Fig-
ure 13-3 and Figure 13-4. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing Table 13-2 and Table 13-3, as done below:
Figure 13-3. SPI Transfer Format with CPHA = 0
Figure 13-4. SPI Transfer Format with CPHA = 1
Table 13-5.
CPOL Functionality
Leading Edge
Trailing Edge
SPI Mode
CPOL=0, CPHA=0
Sample (Rising)
Setup (Falling)
0
CPOL=0, CPHA=1
Setup (Rising)
Sample (Falling)
1
CPOL=1, CPHA=0
Sample (Falling)
Setup (Rising)
2
CPOL=1, CPHA=1
Setup (Falling)
Sample (Rising)
3
Bit 1
Bit 6
LSB
MSB
SCK (CPOL = 0)
mode 0
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 2
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
MSB first (DORD = 0)
LSB first (DORD = 1)
SCK (CPOL = 0)
mode 1
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 3
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
MSB first (DORD = 0)
LSB first (DORD = 1)



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