AT45DB161D datasheet(2/56 Pages) ATMEL

2 / 56 page

3500M–DFLASH–04/09

AT45DB161D

address lines and a parallel interface, the DataFlash uses a RapidS serial interface to sequen-

tially access its data. The simple sequential access dramatically reduces active pin count,

facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces

package size. The device is optimized for use in many commercial and industrial applications

where high-density, low-pin count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the AT45DB161D does not require high input

voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V

to 3.6V, for both the program and read operations. The AT45DB161D is enabled through the

chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),

Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

2. Pin Configurations and Pinouts

Note:

1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND.

Figure 2-1.

TSOP Top View: Type 1

Figure 2-2.

BGA Package Ball-out

(Top View)

Figure 2-3.

MLF (VDFN) Top View

Figure 2-4.

SOIC Top View

RDY/BUSY

RESET

VCC

GND

SCK

VCC

GND

SCK

RDY/BSY

RESET

SCK

RESET

GND

VCC

SCK

RESET

GND

VCC

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