ICS8430002AY REVISION C NOVEMBER 12, 2009

6

©2009 Integrated Device Technology, Inc.

ICS8430002 Data Sheet

HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

27

S_DATA

Input

Pulldown

Shift register serial input. Data sampled on the rising edge of S_CLOCK.

LVCMOS/LVTTL interface levels.

28

S_LOAD

Input

Pulldown

Controls transition of data from shift register into the dividers.

LVCMOS/LVTTL interface levels.

29

Power

Analog supply pin.

30

SEL

Input

Pulldown

Selects between the crystal oscillator or the PCLK/nPCLK inputs as the PLL

reference source. Selects XTAL inputs when LOW. Selects PCLK/nPCLK when

HIGH. LVCMOS/LVTTL interface levels.

33,

34

XTAL_IN

XTAL_OUT

Input

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

37

PCLK

Input

Pulldown

Non-inverting differential clock input.

38

nPCLK

Input

Pullup/

Pulldown

39

nP_LOAD

Input

Pulldown

Parallel load input. Determines when data present at M5:M0 is loaded into M

divider, and when data present at NA2:NA0 and NB2:NB0 is loaded into the N

output divider value. LVCMOS/LVTTL interface levels.

40

VCO_SEL

Input

Pullup

Determines whether the synthesizer is in PLL or Bypass mode. LVCMOS/LVTTL

interface levels.

41, 42, 43,

44, 45

M0, M1, M2,

M3, M4

Input

Pulldown

M divider integer inputs. The fractional portion of M divider can only be

programmed by serial interface. Data latched on LOW-to-HIGH transition of

nP_LOAD input. LVCMOS/LVTTL interface levels.

46

M5

Input

Pullup

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k

Ω

51

k

Ω

Output Impedance

REF_OUT

7

Ω

Number

Name

Type

Description