ICS8430002 datasheet(4/27 Pages) IDT

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ICS8430002AY REVISION C NOVEMBER 12, 2009

ICS8430002 Data Sheet

HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER

Assuming a 25MHz reference frequency and a VCO frequency of

637.5MHz (which, with an output divider of 6 would give an output

frequency of 106.25MHz, a common Fibre channel reference

frequency), requires an M setting of 25.5 (the integer portion being

25 and the fractional portion being 2048/4096). If you decrease the

fractional portion of the M divider by one bit (from 2048 to 2047), the

frequency change in ppm is calculated by:

Which, for these conditions, is a step size of 9.6 ppm.

The ICS8430002 supports either serial or parallel programming

modes to program the P pre-divider, M feedback divider and N output

divider, however the parallel interface can only program the integer

portion of the feedback divider. The fractional portion of the feedback

divider must be programmed serially. Figure 1 shows the timing

diagram for each mode. In parallel mode, the nP_LOAD input is

initially LOW. The data on the M, NA, and NB inputs are passed

directly to the M divider and both N output dividers. On the

LOW-to-HIGH transition of the nP_LOAD input, the data is latched

and the M and N dividers remain loaded until the next LOW transition

on nP_LOAD or until a serial event occurs. As a result, the M and Nx

bits can be hardwired to set the M divider and Nx output divider to a

specific default state that will automatically occur during power-up.

The TEST output is LOW when operating in the parallel input mode.

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA bits with

the rising edge of S_CLOCK. The contents of the shift register are

loaded into the P pre-divider, M divider and Nx output divider when

S_LOAD transitions from LOW-to-HIGH. The P pre-divider, M divider

and Nx output divider values are latched on the HIGH-to-LOW

transition of S_LOAD. The serial mode can be used to program the

P, M and Nx bits and test bits T1 and T0. The data bits are clocked in

the following order as in the table below.

Figure 1. Parallel & Serial Load Operations

stepsize

25.5 25.499755859375

–

()

25.5

----------------------------------------------------------------

×10

ppm

NB2

NB1

NB0

NA2

NA1

NA0

DS1

DS0

MFRAC11 MFRAC10

MFRAC9MFRAC8MFRAC7MFRAC6MFRAC5MFRAC4MFRAC3MFRAC2MFRAC1MFRAC0

MINT5MINT4MINT3MINT2MINT1MINT0

SERIAL LOADING

PARALLEL LOADING

M, N, P

Time

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

S_LOAD

nP_LOAD

M[5:0], NX[2:0], P[2:0]

. . .

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