TLE8201R datasheet(20/45 Pages) INFINEON

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TLE 8201R

Data Sheet Rev. 2.0

2006-06-07

4.3.4

Status Register Address selection and Reset

The SPI is using a standard shift-register concept with daisy-chain capability. Any data

transmitted to the SPI will be available to the internal logic part at the end of the SPI

transmission (CSN L -> H). To read a specific register, the address of the register is sent

by the master to the SPI in a first SPI frame. The data that corresponds to this address

is transmitted by the SPI DO during the following (second) SPI frame to the master. The

default address for Status Register transmission after Power-ON Reset is 00.

The Status-Register-Reset command-bit is executed after the next SPI transmission.

The three bits RA_0, RA_1 and SRR act as command to read and reset (or not reset)

the addressed Status-Register. This is also explained in Figure 5.

The TSD status bit is not part of the adressable data but of the address independent

data. When any of the status registers is reset, the TSD bit is reset, too.

Figure 5

Status Register Addressing and Reset

CSN

Com-

ment

Status Register 01 is transferred to

SPI master, but not reset after

transmission

Status Register 10 is transferred to

SPI master, and reset after

transmission

StatReg10 is reset

after CSN

L->H

After Power-ON Reset, Status

x x x x x

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