PCIMX512CJM6C datasheet(58/184 Pages) FREESCALE

58 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Figure 33. DDR2 SDRAM Write Cycle

Table 47. DDR2 SDRAM Write Cycle

PARAMETER

Symbol

SDCLK = 200 MHz

Unit

Min

Max

DDR17

DQ and DQM setup time to DQS (differential strobe)1

1 These values are for DQ/DM slew rates of 1 V/ns and DQS/DQS_B differential slew rates of 2 V/ns. For different values use

derating table below

tDS(base)

0.15

—

DDR18

DQ and DQM hold time to DQS (differential strobe)

tDH(base)

0.275

—

DDR17

DQ and DQM setup time to DQS (single-ended strobe)2

2 These values are for DQ/DM slew rates of 1 V/ns and DQS slew rates of 1 V/ns. For different values use derating table below

tDS1(base)

0.025

—

DDR18

DQ and DQM hold time to DQS

(single-ended strobe)2

tDH1(base)

0.025

—

DDR19

Write cycle DQS falling edge to SDCLK output setup time

tDSS

0.2

—

tCK

DDR20

Write cycle DQS falling edge to SDCLK output hold time

tDSH

0.2

—

tCK

DDR21

DQS latching rising transitions to associated clock edges

tDQSS

–0.25

0.25

tCK

DDR22

DQS high level width

tDQSH

0.35

—

tCK

DDR23

DQS low level width

tDQSL

0.35

—

tCK

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

Data

DDR17

DDR18

DDR19

DDR20

DDR21

DDR23

DDR22

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