MPC5643L datasheet(19/98 Pages) FREESCALE

19 / 98 page

Overview

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1.3.33

Analog-to-Digital Converter module (ADC)

The ADC module features are as follows:

Analog part:

•

Two on-chip ADCs

— 12-bit resolution SAR architecture

— Same digital interface as in the MPC5604P family

— A/D Channels: Nine external, Three internal and Four shared with other A/D. Total 16

— One channel dedicated to each T-sensor to enable temperature reading during application

— Separated reference for each ADC

— Shared analog supply voltage for both ADCs

— One sample and hold unit per ADC

— Adjustable sampling and conversion time

Digital part:

•

Four analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored

in the appropriate ADC result location

•

Two modes of operation: Motor Control Mode or Regular Mode

•

Regular mode features

— Register based interface with the CPU: one result register per channel

— ADC state machine managing three request flows: regular command, hardware injected command, software

injected command

— Selectable priority between software and hardware injected commands

— Four analog watchdogs comparing ADC results against predefined levels (low, high, range)

— DMA compatible interface

•

Motor control mode features

— Triggered mode only

— Four independent result queues (1

× 16 entries, 2 × 8 entries, 1 × 4 entries)

— Result alignment circuitry (left justified; right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit parts

— DMA compatible interfaces

•

Built-in self-test features triggered by software

1.3.34

Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without

CPU load during the PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:

•

Cross triggering between ADC, FlexPWM, eTimer, and external pins

•

Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers

•

Maximum operating frequency less than or equal to 120 MHz

•

Trigger generation unit configurable in sequential mode or in triggered mode

•

Trigger delay unit to compensate the delay of external low pass filter

•

Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

•

Double buffered ADC command list pointers to minimize ADC-trigger unit update

•

Double buffered ADC conversion command list with as many as 24 ADC commands

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