MPC5643L datasheet(25/98 Pages) FREESCALE

25 / 98 page

Package pinouts and signal descriptions

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

2.2

Pin descriptions

The following sections provide signal descriptions and related information about the functionality and configuration for this

device.

2.2.1

Concatenated pins

Table 3 provides the concatenated ball names (pin muxing) for the pins shown in Figure 2 and the balls shown in Figure 3,

including the functional group for the pin. This table provides a cross-reference for the two packages. Table 3 lists the

concatenated ball names (pin muxing) in alphanumeric order for the balls shown in Figure 3, including the functional group.

Table 3. Concatenated pin names

No.

144

LQFP

Ball

No.

257

MAPBGA

Concatenated Pin Names

1E4

NMI

A[6] / siul_GPIO[6] / dspi1_SCK / siul_EIRQ[6]

D[1] / siul_GPIO[49] / etimer1_ETC[2] / ctu0_EXT_TGR / flexray_CA_RX

F[4] / siul_GPIO[84] / npc_wrapper_MDO[3]

F[5] / siul_GPIO[85] / npc_wrapper_MDO[2]

6VDD_HV1 VDD_HV_IO

VSS_HV2 VSS_HV_IO

F[6] / siul_GPIO[86] / npc_wrapper_MDO[1]

9E1

MDO0

A[7] / siul_GPIO[7] / dspi1_SOUT / siul_EIRQ[7]

C[4] / siul_GPIO[36] / dspi0_CS0 / flexpwm0_X[1] / sscm_DEBUG[4] / siul_EIRQ[22]

A[8] / siul_GPIO[8] / dspi1_SIN / siul_EIRQ[8]

C[5] / siul_GPIO[37] / dspi0_SCK / sscm_DEBUG[5] / flexpwm0_FAULT[3] / siul_EIRQ[23]

A[5] / siul_GPIO[5] / dspi1_CS0 / etimer1_ETC[5] / dspi0_CS7 / siul_EIRQ[5]

C[7] / siul_GPIO[39] / flexpwm0_A[1] / sscm_DEBUG[7] / dspi0_SIN

VDD_HV_REG_0

VSS_LV3 VSS_LV_COR

VDD_LV4 VDD_LV_COR

F[7] / siul_GPIO[87] / npc_wrapper_MCKO

F[8] / siul_GPIO[88] / npc_wrapper_MSEO[1]

VDD_HV3 VDD_HV_IO

VSS_HV4 VSS_HV_IO

F[9] / siul_GPIO[89] / npc_wrapper_MSEO[0]

F[10] / siul_GPIO[90] / npc_wrapper_EVTO

F[11] / siul_GPIO[91] / leo_sor0_EVTI

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