SC9RS08KA2J3CSC datasheet(99/134 Pages) FREESCALE

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Chapter 12 Development Support

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Figure 12-2. Standard RS08 BDM Tool Connector

Background debug controller (BDC) serial communications use a custom serial protocol that was first

introduced on the M68HC12 Family of microcontrollers. This protocol requires that the host knows the

communication clock rate, which is determined by the target BDC clock rate. If a host is attempting to

communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to

the target MCU to request a timed sync response signal from which the host can determine the correct

communication speed.

For RS08 MCUs, the BDC clock is the same frequency as the MCU bus clock. For a detailed description

of the communications protocol, refer to Section 12.3.2, “Communication Details."

12.3.1

BKGD Pin Description

BKGD is the single-wire background debug interface pin. BKGD is a pseudo-open-drain pin that contains

an on-chip pullup, therefore it requires no external pullup resistor. Unlike typical open-drain pins, the

external resistor capacitor (RC) time constant on this pin, which is influenced by external capacitance,

plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup

pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to

Section 12.3.2, “Communication Details," for more detail.

The primary function of this pin is bidirectional serial communication of background debug commands

and data. During reset, this pin selects between starting in active background mode and normal user mode

running an application program. This pin is also used to request a timed sync response pulse to allow a

host development tool to determine the target BDC clock frequency.

By controlling the BKGD pin and forcing an MCU reset (issuing a BDC_RESET command, or through a

power-on reset (POR)), the host can force the target system to reset into active background mode rather

than start the user application program. This is useful to gain control of a target MCU whose FLASH

program memory has not yet been programmed with a user application program.

When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD

determines the normal operating mode.

On some RS08 devices, the BKGD pin may be shared with an alternative output-only function. To support

BDM debugging, the user must disable this alternative function. Debugging of the alternative function

must be done in normal user mode without using BDM.

12.3.2

Communication Details

The BDC serial interface requires the host to generate a falling edge on the BKGD pin to indicate the start

of each bit time. The host provides this falling edge whether data is transmitted or received.

RESET/VPP

BKGD

GND

NO CONNECT

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