SC9RS08KA2 datasheet(76/134 Pages) FREESCALE

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Internal Clock Source (RS08ICSV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

9.1.1

Features

Key features of the ICS module are:

•

Frequency-locked loop (FLL) is trimmable for accuracy

— 0.2% resolution using internal 32 kHz reference

— 2% deviation over voltage and temperature using internal 32 kHz reference

— DCO output is 512 times internal reference frequency

•

Internal reference clock has 9 trim bits available

•

Internal reference clock can be selected as the clock source for the MCU

•

Whichever clock is selected as the source can be divided down

— 2 bit select for clock divider is provided (allowable dividers are: 1, 2, 4, and 8)

•

FLL engaged internal mode is automatically selected out of reset

9.1.2

Modes of Operation

There are four modes of operation for the ICS: FEI, FBI, FBILP, and stop.

9.1.2.1

FLL Engaged Internal (FEI)

In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL

which is controlled by the internal reference clock.

9.1.2.2

FLL Bypassed Internal (FBI)

In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is

bypassed. The ICS supplies a clock derived from the internal reference clock.

9.1.2.3

FLL Bypassed Internal Low Power (FBILP)

In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock

derived from the internal reference clock.

9.1.2.4

Stop (STOP)

In stop mode, the FLL is disabled and the internal reference clocks can be selected to be enabled or

disabled. The ICS does not provide an MCU clock source.

9.1.3

Block Diagram

Figure 9-2 shows the ICS block diagram.

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