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STM8L151C4T3 bảng dữ liệu(PDF) 58 Page - STMicroelectronics |
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STM8L151C4T3 bảng dữ liệu(HTML) 58 Page - STMicroelectronics |
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58 / 101 page ![]() Electrical parameters STM8L151xx, STM8L152xx 58/101 Doc ID 15962 Rev 2 8.3 Operating conditions Subject to general operating conditions for VDD and TA. 8.3.1 General operating conditions Table 15. General operating conditions Symbol Parameter Conditions Min Max Unit fSYSCLK (1) System clock frequency 1.65 V ≤VDD < 3.6 V 0 16 MHz VDD Standard operating voltage 1.65(2) 3.6 V VDDA Analog operating voltage ADC not used Must be at the same potential as VDD 1.65(2) 3.6 V ADC used 1.8 3.6 V PD (3) Power dissipation at TA= 85 °C for suffix 6 devices VFQFPN48 (4) TBD mW LQFP48 TBD WFQFPN32 (5) TBD LQFP32 TBD WFQFPN28 (6) TBD Power dissipation at TA= 125 °C for suffix 3 devices VFQFPN48(4) TBD LQFP48 TBD WFQFPN32(5) TBD LQFP32 TBD WFQFPN28(6) TBD TA Temperature range 1.65 V ≤VDD < 3.6 V (6 suffix version) -40 85 °C 1.65 V ≤VDD < 3.6 V (3 suffix version) -40 125 TJ Junction temperature range -40 °C ≤TA < 85 °C (6 suffix version) -40 105 °C -40 °C ≤ TA < 125 °C (3 suffix version) -40 130 1. fSYSCLK = fCPU 2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled. 3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ Θ JA with TJmax in this table and Θ JA in “Thermal characteristics” table. 4. VFQFPN48 package is used in the sampling phase. In the production phase, the UFQFPN48 package will be used (with a thickness equal to 0.6 mm). 5. WFQFPN32 package is used in the sampling phase. In the production phase, the UFQFPN32 package will be used (with a thickness equal to 0.6 mm). 6. WFQFPN28 package is used in the sampling phase. In the production phase, the UFQFPN28 package will be used (with a thickness equal to 0.6 mm). |
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