STM32F103XC datasheet(82/123 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

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Doc ID 14611 Rev 7

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL

compliant.

Table 44.

Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA +105 °C conforming to JESD78A

II level A

Table 45.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

TTL ports

–0.5

0.8

VIH

Standard IO input high level voltage

VDD+0.5

IO FT(1) input high level voltage

5.5V

VIL

Input low level voltage

CMOS ports

–0.5

0.35 VDD

VIH

Input high level voltage

0.65 VDD

VDD+0.5

Vhys

Standard IO Schmitt trigger voltage

hysteresis(2)

200

IO FT Schmitt trigger voltage

hysteresis(2)

5% VDD

(3)

Ilkg

Input leakage current (4)

VSS  VIN  VDD

Standard I/Os

1

µA

VIN= 5 V, I/O FT

RPU

Weak pull-up equivalent resistor(5)

VIN VSS



RPD

Weak pull-down equivalent resistor(5)

VIN VDD



CIO

I/O pin capacitance

FT = Five-volt tolerant.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

With a minimum of 100 mV.

Leakage could be higher than max. if negative current is injected on adjacent pins.

Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

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