XRT86VL32IB datasheet(45/154 Pages) EXAR

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XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

If the Receive Data Link Source Select bits of the Receive Data Link Select Register are set to 10, the Receive

Overhead Output Interface Block becomes Output source of the FDL bits.

The XRT86VL3x allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format

mode. The FDL can be either a 4KHz or 2KHz data link channel. The Receive Data Link Bandwidth Select bits

of the Receive Data Link Select Register (RDLSR) determine the bandwidth of FDL channel in ESF framing

format mode.

The table below shows configuration of the Receive Data Link Bandwidth Select bits of the Receive Data Link

Select Register (TDLSR).

Figure 39 below shows the timing diagram of the Output and output signals associated with the DS1 Receive

Overhead Output Interface module in ESF framing format mode.

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

1-0

Receive Data Link

Destination Select

R/W

00 - The extracted Facility Data Link bits are stored in either the LAPD con-

troller or the SLC®96 buffer. At the same time, the extracted Facility Data

Link bits are outputted from the framer through the Receive Serial Data

Output Interface via the RxSer_n pins.

01 - The extracted Facility Data Link bits are outputted from the framer

through the Receive Serial Data Output Interface via the RxSer_n pins.

10 - The extracted Facility Data Link bits are outputted from the framer

through the Receive Overhead Output Interface via the RxOH_n pins. At

the same time, the extracted Facility Data Link bits are outputted from the

framer through the Receive Serial Data Output Interface via the RxSer_n

pins.

11 - The Facility Data Link bits are forced to one by the framer.

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)

BIT

NUMBER

BIT NAME

BIT TYPE

BIT DESCRIPTION

5-4

Receive Data Link

Bandwidth Select

R/W

00 - The Facility Data Link is a 4KHz channel. All available FDL bits (first

bit of every other frame) are used as data link bits.

01 - The Facility Data Link is a 2KHz channel. Only the odd FDL bits (first

bit of frame 1, 5, 9…) are used as data link bits.

10 - The Facility Data Link is a 2KHz channel. Only the even FDL bits (first

bit of frame 3, 7, 11…) are used as data link bits.

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