XRT86VL32IB datasheet(19/154 Pages) EXAR

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XRT86VL3X

REV. 1.2.3

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

1.10

Overhead Interface

The Overhead interface provides an option for inserting the datalink bits into the transmit PCM data or

extracting the datalink bits from the receive PCM data. By default, the datalink information is processed to and

from the PCM data directly. On the transmit path, the overhead clock is automatically provided as a clock

reference to externally time the datalink bits. The user should provide data on the rising edge of the TxOHclk

so that the framer can sample the datalink bits on the falling edge. On the receive path, the datalink bits are

updated on the rising edge of the RxOHclk output pin. In T1 ESF mode, a datalink bit occurs every other

frame. Therefore, the default overhead interface is operating at 4kbps. In E1 mode, the datalink bits are

located in the first time slot of each Non-FAS frame. Figure 14 is a simplified block diagram of the Overhead

Interface.

Figure 15 is a simplified diagram for the T1 external overhead datalink bus.

Figure 16 is a

simplified diagram for the E1 external overhead datalink bus.

FIGURE 13. SF / SLC-96 OR 4-CODE SIGNALING IN ESF / CAS EXTERNAL SIGNALING BUS

FIGURE 14. T1/E1 OVERHEAD INTERFACE

TxSYNC

TxMSYNC

TxSERclk

TxCHN0/TxSIG

TxSER

TS 1

TS 2

TS 3

Datalink Bits

PCM Data

Tx LIU

Rx LIU

Datalink Bits

PCM Data

Transmit Direction

Receive Direction

TxSER

TxOH

RxSER

RxOH

Physical

Interface

TxOHclk

RxOHclk

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