TMC2192 datasheet(13/69 Pages) CADEKA

13 / 69 page

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Figure 8. Horizontal Timing

Vertical interval timing is also fully programmable, and is

established by loading the timing registers with the dura-

tion’s of each vertical timing element, the duration expressed

in PCK clock cycles. In this way as with horizontal program-

ming, any pixel rate between 10 and 15 Mpps can be accom-

modated, and any desired standard or non-standard vertical

video timing may be produced.

Like horizontal timing parameters, vertical timing parame-

ters are calculated as follows:

t = N x ( PCK period )

= N x ( 2 x PXCK period )

where N is the value loaded into the appropriate timing reg-

ister, and PCK is the pixel clock period.

The vertical interval comprises several different line types

based upon H, the Horizontal line time.

H = (2 x SL) + (2 x SH) [Vertical sync pulses]

= (2 x EL) + (2 x EH) [Equalization pulses]

Figure 9. Horizontal Timing – Vertical Blanking

The VB and VC control registers are added to produce the

half-lines needed in the vertical interval at the beginning and

end of some ﬁelds. These must properly mate with compo-

nents of the normal lines.

CBP

65-6294-10

Table 5. Horizontal Timing Speciﬁcations

Parameter

NTSC-M

(

µs)

PAL-I

(

µs)

PAL-M

(

µs)

1.5

1.65

1.9

4.7

4.95

0.6

0.9

2.5

2.25

CBP

1.6

2.55

1.8

52.6556

51.95

51.692

63.5556

64.0

63.492

H/2

65-6294-11

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