REV. 1B October 2003

7

SPT7851

DATA SHEET

Clock

The SPT7851 accepts a low voltage CMOS logic level at

the CLK input. The duty cycle of the clock should be kept as

close to 50% as possible. Because consecutive stages in the

ADC are clocked in opposite phase to each other, a non-50%

duty cycle reduces the settling time available for every other

stage and thus could potentially cause a degradation of

dynamic performance.

For optimal performance at high input frequencies, the clock

should have low jitter and fast edges. The rise/fall times

should be kept shorter than 2ns. Overshoot and undershoot

should be avoided. Clock jitter causes the noise floor to rise

proportional to the input frequency. Because jitter can be

caused by crosstalk on the PC board, it is recommended that

the clock trace be kept as short as possible and standard

transmission line practices be followed.

Digital Outputs

The digital output data appears in an offset binary code at

3.3V CMOS logic levels. A negative full scale input results

in an all zeros output code (000…0). A positive full scale

input results in an all 1’s code (111…1). The output data is

available 7.5 clock cycles after the data is sampled. The input

signal is sampled on the high to low transition of the input

clock. Output data should be latched on the low to high clock

transition as shown in figure 1, the Timing Diagram. The

output data is invalid for the first 20 clock cycles after the

device is powered up.

Evaluation Board

The EB7851 Evaluation Board is available to aid designers

in demonstrating the full performance capability of the

SPT7851. The board includes an on-board clock driver,

adjustable voltage references, adjustable bias current

circuits, single-to-differential input buffers with adjustable

levels, a single-to-differential transformer (1:1), digital

output buffers and 3.3/5 V adjustable logic outputs. An

application note (AN7851) is also available which describes

the operation of the evaluation board and provides an

example of the recommended power and ground layout and

signal routing. Contact the factory for price and availability.

Pin Configuration

D8

D9 (MSB)

GND

CLK

N/C

VDD3

VDD2

VDD2

VDD1

VDD1

VDD1

VREF–

VREF+

1

2

3

4

5

6

7

8

9

10

11

GND

GND

GND

GND

GND

GND

GND

GND

GND

33

32

31

30

29

28

27

26

25

24

23

Pin Assignments

Pin Name

Description

Analog Inputs

External Reference Inputs

CLK

Input Clock

Common Mode Output Voltage (1.65V typ)

Bias1

Bias Current (90µA typ)

Bias2

Bias Current (9.5µA typ)

D0 – D9

Digital Outputs (D0 = LSB)

GND

Analog Ground

Analog Power Supply

Digital Power Supply

Digital Output Power Supply

N/C

No connect

DNC

Do not connect pins; leave floating