REV. 1B October 2003

5

SPT7851

DATA SHEET

General Description

The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC.

It has a pipelined architecture and incorporates digital error

correction of all 10 bits. This error correction ensures good

linearity performance for input frequencies up to Nyquist.

The inputs are fully differential, making the device insensi-

tive to system-level noise. This device can also be used in a

single-ended mode. (See analog input section.) With the

power dissipation roughly proportional to the sampling rate,

this device is ideal for very low power applications in the

range of 1 to 20 MSPS.

Typical Interface Circuit

The SPT7851 requires few external components to achieve

the stated operation and performance. Figure 2 shows the

typical interface requirements when using the SPT7851

in normal circuit operation. The following sections provide

a description of the functions and outline critical perfor-

mance criteria to consider for achieving the optimal device

performance.

N+8

N+7

N+6

N+2

N+1

N

N-1

N-2

N-1

N

Sampling

Points

CLK

Figure 1: Timing Diagram

GND

.01 µF

+

4.7 µF

Ref- In

(+1.15 V)

Ref+ In

(+2.15 V)

.01 µF

+

10 µF

0.1 µF

+3.3V

(3V Logic)

Interfacing

3V Logic

Decoupling

Cap

DGND

FB

AGND

U1

SPT7851

.01 µF

(+1.65 V)

Minicircuit

T1-6T

51Ω

68 pF

22

23

11

12

34

33

1

44

N/C

N/C

N/C

GND

Bias1

Bias2

VCM

GND

VIN+

VIN-

GND

D0

D1

D2

D3

D4

D5

D6

D7

.01 µF

+

4.7 µF

+3.3V Digital

9.5 µA

90 µA

DNC

DNC

(LSB)

2. FB = Ferrite Bead; must be placed as close to U1 as possible.

+3.3V

Figure 2: Typical Interface Circuit