SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

Page 7 of 45

This section describes the MOSI transfer.

To extend the setup time, set the timing between the master output and slave input (latch data) as one cycle of the RSPCK.

As the serial flash memory used in this application latches data on the rising edge, the SH7264 must outputs data on the

preceding rising edge.

There are two combinations of options for bit setting as (CPOL = 1, CPHA =0) or (CPOL = 0, CPHA = 1) for the master to

output data on the rising edge. This example uses (CPOL = 1, CPHA = 0) for the following reason.

When setting the CPHA bit to 1, the master (SH7264) outputs the first data bit on the first RSPCK edge (on the rising edge

when the CPOL bit is 0), not upon asserting SSL signal. And the slave (serial flash memory) latches data on the first rising

edge. Therefore, when setting the CPOL bit to 0, and the CPHA bit to 1, the slave latches data when the master outputs the

first bit of data. This setting does not satisfy the setup condition.

When using the setting (CPOL =1, CPHA = 0), the master outputs the first data bit upon asserting SSL signal. There is more

than one cycle before the first rising edge of the RSPCK, the timing when the slave latches data. This setting satisfies the

setup condition. From the second data bit, the master outputs data on the rising edge of the RSPCK, and the slave latches

data on the next rising edge to satisfy the timing condition. The following figure shows the MOSI transfer timing when

setting (CPOL = 1, CPHA = 0).

SSL00

MOSI0

Master outputs the first data bit

RSPCK0

Set the RSPI as (CPOL = 1, CPHA = 0)

- Specify the RSPCK as 1 when idle

- Output data on the even edge

- Output the first data bit upon asserting SSL

Master outputs the

second data bit

The master must output data on rising edge of the RSPCK to

ensure one cycle before the timing when the slave latches data.

->Use the setting (CPOL = 1, CPHA = 0) or (CPOL = 0, CPHA = 1).

Serial flash memory latches

data on rising edge.

1

2

RSPCK

frequency

Set the RSPI as CPHA = 0 to

output data upon asserting

SSL.

Figure 4 Interface Timing on MOSI Transfer