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CY7C68053
Document # 001-06120 Rev *I
Page 25 of 40
9. AC Electrical Characteristics
9.1 USB Transceiver
USB 2.0-compliant in full and high speed modes.
9.2 GPIF Synchronous Signals
8
DATA(output)
tXGD
IFCLK
RDYX
DATA(input)
valid
tSRY
tRYH
tIFCLK
tSGD
CTLX
tXCTL
tDAH
N
N+1
GPIFADR[8:0]
tSGA
Figure 8. GPIF Synchronous Signals Timing Diagram[16]
Table 10.GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[16,17]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
ns
tSRY
RDYX to clock setup time
8.9
ns
tRYH
Clock to RDYX
0ns
tSGD
GPIF data to clock setup time
9.2
ns
tDAH
GPIF data hold time
0
ns
tXGD
Clock to GPIF data output propagation delay
11
ns
tXCTL
Clock to CTLX output propagation delay
6.7
ns
Notes
16. Dashed lines denote signals with programmable polarity.
17. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
18. IFCLK must not exceed 48 MHz.
Table 11.GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[17]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period[18]
20.83
200
ns
tSRY
RDYX to clock setup time
2.9
ns
tRYH
Clock to RDYX
3.7
ns
tSGD
GPIF data to clock setup time
3.2
ns
tDAH
GPIF data hold time
4.5
ns
tXGD
Clock to GPIF data output propagation delay
15
ns
tXCTL
Clock to CTLX output propagation delay
13.06
ns
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