CY7C68053
Document # 001-06120 Rev *I
Page 14 of 40
PORT D
8A
PD0 or
FD[8]
I/O/Z
I
(PD0)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
7A
PD1 or
FD[9]
I/O/Z
I
(PD1)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
6B
PD2 or
FD[10]
I/O/Z
I
(PD2)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
6A
PD3 or
FD[11]
I/O/Z
I
(PD3)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
3B
PD4 or
FD[12]
I/O/Z
I
(PD4)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
3A
PD5 or
FD[13]
I/O/Z
I
(PD5)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
3C
PD6 or
FD[14]
I/O/Z
I
(PD6)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
2A
PD7 or
FD[15]
I/O/Z
I
(PD7)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
1A
RDY0 or
SLRD
Input
N/A
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY0 is a GPIF input signal.
SLRD is the input only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0].
1B
RDY1 or
SLWR
Input
N/A
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY1 is a GPIF input signal.
SLWR is the input only write strobe with programmable polarity (FIFOPIN-
POLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0].
7H
CTL0 or
FLAGA
O/Z
H
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
7G
CTL1 or
FLAGB
O/Z
H
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
8H
CTL2 or
FLAGC
O/Z
H
Multiplexed pin whose function is selected IFCONFIG[1:0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
2G
IFCLK
I/O/Z
Z
Interface clock, used to synchronous clock data into or out of the slave FIFOs.
IFCLK also serves as a timing reference for all slave FIFO control signals and
GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be
configured to output 30 or 48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK
may be inverted, whether internally or externally sourced, by setting the bit
IFCONFIG.4 =1.
Table 7. FX2LP18 Pin Descriptions (continued)[9]
56 VFBGA
Name
Type
Default
Description
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