STA2500DTR datasheet(9/57 Pages) STMICROELECTRONICS

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STA2500D

Quick reference data

Doc ID 16067 Rev 1

9/57

Table 8.

System clock, sine wave specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

VPP

Peak to peak voltage range

0.27

0.5

1.8

Total harmonic content of input signal

-25

dBc

ZINRe

Real part of parallel input impedance at pin

ZINIm

Imaginary part of parallel input impedance at pin

ZIDRe

Real impedance discrepancy between active and non-

active mode of clock input

ZIDim

Imaginary impedance discrepancy between active and

non-active mode of clock input

500

Phase noise @ 10 kHz(1)

-126

dBc/Hz

Equivalent to max 10 ps time jitter (rms).

Table 9.

System clock, digital clock DC specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

VIL

Low level input voltage

-0.2

0.35 *

BT_VDD_CLD

VIH

High level input voltage

0.65 *

BT_VDD_CLD

(BT_VDD_CLD

+ 0.2) and

(

≤ 2.85)

CIN

Input capacitance

Table 10.

System clock, digital clock AC specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRISE

10% - 90% rise time

1.5

TFALL

90% - 10% fall time

1.5

DCYCLE

Duty cycle

Phase noise @ 10 kHz(1)

-121

dBc/Hz

Equivalent to max 15 ps time jitter (rms).

Table 11.

Low power clock specifications

The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.

Symbol

Parameter

Min.

Typ.

Max.

Unit

FIN

Clock input frequencies

3.2, 32, 32.768

kHz

Duty cycle

Tolerance on input frequency

−250

250

ppm

VIL

Low level input voltage

0.35 *

BT_VIO_B

VIH

High level input voltage

0.65 *

BT_VIO_B

Vhyst

Schmitt trigger hysteresis (BT_VIO_B = 1.8 V)

0.4

0.5

0.6

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