TMS320UC5402 datasheet(2/63 Pages) TI

2 / 63 page

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

description (continued)

Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply.

However, systems should be designed to ensure that neither supply is powered up for extended periods of time

if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely

affect the long term reliability of the device.

System-level concerns such as bus contention may require supply sequencing to be implemented. In this case,

the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down after

the I/O buffers.

The ’UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and

three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of

parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis

of the operational flexibility and speed of this DSP is a highly specialized instruction set.

NOTE: For detailed information on the architecture of the ’C5000 family of DSPs, see the

TMS320C5000 DSP Family

Functional Overview (literature number SPRU307).

TMS320UC5402 bảng dữ liệu(PDF) 2 Page - Texas Instruments