TMS320F241FN datasheet(58/66 Pages) TI

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TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

internal ADC module timings (see Figure 32)

MIN

MAX

UNIT

tc(AD)

Cycle time, ADC prescaled clock

tw(SHC)

Pulse duration, total sample/hold and conversion time†

900

tw(SH)

Pulse duration, sample and hold time

3tc(AD)

tw(C)

Pulse duration, total conversion time

10tc(AD)

td(SOC-SH)

Delay time, start of conversion‡ to beginning of sample and hold

3tc(CO)

td(EOC-FIFO)

Delay time, end of conversion to data loaded into result FIFO

2tc(CO)

td(ADCINT)

Delay time, ADC flag to ADC interrupt

2tc(CO)

† The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC-FIFO).

‡ Start of conversion is signaled by the ADCIMSTART bit (ADCTRL1.13) or the ADCSOC bit (ADCTRL1.0) set in software, the external start signal

active (ADCSOC), or internal EVSOC signal active.

tw(C)

tc(AD)

ADC Clock

Analog Input

Bit Converted

td(SOC–SH)

EOC/Convert

Internal Start/

Sample Hold

Start of Convert

XFR to FIFO

tw(SHC)

td(EOC–FIFO)

tw(SH)

td(ADCINT)

Figure 32. Analog-to-Digital Internal Module Timing

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