THS5641A

8-BIT, 100 MSPS, CommsDAC

™

DIGITAL-TO-ANALOG CONVERTER

SLAS277 –MARCH 2000

13

POST OFFICE BOX 655303

APPLICATION INFORMATION

The THS5641A architecture is based on current steering, combining high update rates with low power

consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are

capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current

of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents

thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc

offsets, even order distortion components, and increase signal output power by a factor of two. Major

advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic

performance. The DAC’s high output impedance of >300 k

Ω and fast switching result in excellent dynamic

linearity (spurious free dynamic range SFDR).

from 20 mA down to 2 mA.

data interface and timing

supply voltage can be set independently from 5.5 V down to 3 V. The THS5641A provides two operating modes,

as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format,

Figure 23 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge

of the input clock. The THS5641A provides for minimum setup and hold times (> 1 ns), allowing for noncritical

external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be

chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle

will give optimum dynamic performance. Figure 24 shows a schematic of the equivalent digital inputs of the

THS5641A, valid for pins D7–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic

the clock and data input signals are important in achieving the optimum performance. The drivers of the digital

data interface circuitry should be specified to meet the minimum setup and hold times of the THS5641A, as well

as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that

satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the