THS5641AIPW datasheet(6/28 Pages) TI

6 / 28 page

THS5641A

8-BIT, 100 MSPS, CommsDAC

™

DIGITAL-TO-ANALOG CONVERTER

SLAS277 –MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,

DVDD = 5 V, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless

otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC linearity (to Nyquist)

fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C

fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C

fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C

fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C

fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C

fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C

SFDR

Spurious free dynamic range

fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C

dBc

fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C

fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C

fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C

fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C

fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C

fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Interface

VIH

High level input voltage

DVDD = 5 V

3.5

VIH

High-level input voltage

DVDD = 3.3 V

2.1

3.3

VIL

Low level input voltage

DVDD = 5 V

1.3

VIL

Low-level input voltage

DVDD = 3.3 V

0.9

IIH

High-level input current

DVDD = 3 V to 5.5 V

–10

µA

IIL

Low-level input current

DVDD = 3 V to 5.5 V

–10

µA

Input capacitance

Timing

tsu(D)

Input setup time

th(D)

Input hold time

tw(LPH)

Input latch pulse high time

td(D)

Digital delay time

clk

Specifications subject to change

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