LTC2230UP datasheet(19/32 Pages) LINER

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LTC2230/LTC2231

22301fb

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third and fourth stages, resulting in a fourth

stage residue that is sent to the fifth stage ADC for final

evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2230/

LTC2231 CMOS differential sample-and-hold. The analog

inputs are connected to the sampling capacitors (CSAMPLE)

through NMOS transistors. The capacitors shown at-

tached to each input (CPARASITIC) are the summation of all

other capacitance associated with each input.

During the sample phase when ENC is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to, and track the differential input voltage.

When ENC transitions from low to high, the sampled input

voltage is held on the sampling capacitors. During the hold

phase when ENC is high, the sampling capacitors are

disconnected from the input and the held voltage is passed

to the ADC core for processing. As ENC transitions from

high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitors still hold the previous sample, a charging glitch

proportional to the change in voltage between samples will

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

CSAMPLE

1.6pF

VDD

LTC2230/LTC2231

AIN

22201 F02

CSAMPLE

1.6pF

VDD

AIN

–

ENC–

ENC+

1.6V

CPARASITIC

1pF

CPARASITIC

1pF

Figure 2. Equivalent Input Circuit

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, AIN+

should be driven with the input signal and AIN– should be

connected to 1.6V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing

±0.5V for

the 2V range or

±0.25V for the 1V range, around a

common mode voltage of 1.6V. The VCM output pin (Pin

APPLICATIO S I FOR ATIO

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